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| ds1689/DS1693 3 volt/5 volt serialized real time clock with nv ram control ds1689/DS1693 030598 1/30 features incorporates industry standard ds1287 pc clock plus enhanced features: ? +3 or +5 volt operation ? 64bit silicon serial number ? 64bit customer specific rom or additional serial number available ? power control circuitry supports system power on from date/time alarm or key closure ? automatic battery backup and write protection to external sram ? crystal select bit allows rtc to operate with 6 pf or 12.5 pf crystal ? 114 bytes user nvram ? auxiliary battery input ? ram clear input ? century register ? 32 khz output for power management ? 32bit v cc powered elapsed time counter ? 32bit v bat powered elapsed time counter ? 16bit power cycle counter ? compatible with existing bios for original ds1287 functions ? available as chip (ds1689) or standalone module with embedded battery and crystal (DS1693) ? chips are available in industrial temperature version ? timekeeping algorithm includes leap year compensa- tion valid up to 2100 ordering information part # description ds1689 rtc chip, 28pin dip ds1689s rtc chip, 28pin soic DS1693 rtc module; 28pin dip pin assignment v baux x1 x2 rclr ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 pwr gnd cei ceo v cci v cco sqw v bat irq psel rd gnd wr ale cs ks v baux x1 x2 rclr ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 pwr gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cei ceo v cci v cco sqw v bat irq psel rd gnd wr ale cs ks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ds1689 28-pin dip (600 mil) ds1689s 28-pin soic (330 mil) cei ceo v cci v cco sqw nc irq psel rd nc wr ale cs ks v baux nc nc rclr ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 pwr gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DS1693 28-pin encapsu- lated package (740 mil) pin description x1 crystal input x2 crystal output rclr ram clear input ad0-ad7 mux'ed address/data bus pwr poweron interrupt output (open drain) ks kickstart input cs rtc chip select input ale rtc address strobe wr rtc write data strobe rd rtc read data strobe v cco ram power supply output
ds1689/DS1693 030598 2/30 irq interrupt request output (open drain) sqw square wave output v cci +3 or +5 volt main supply gnd ground v bat battery + supply v baux auxiliary battery supply psel +3 or +5 volt power select cei ram chip enable in ceo ram chip enable out description the ds1689/DS1693 is a real time clock (rtc) de- signed as a successor to the industry standard ds1285, ds1385, ds1485, and ds1585 pc real time clocks. this device provides the industry standard ds1285 clock function with the new feature of either +3.0 or +5.0 volt operation and automatic backup and write protec- tion to an external sram. the ds1689 also incorpo- rates a number of enhanced features including a silicon serial number, power on/off control circuitry, 114 bytes of user nvsram, power on elapsed timer, and power cycle counter. each ds1689/DS1693 is indivi dually manufactured with a unique 64bit serial number as well as an additional 64bit customer specific rom or serial number. the seri- al number is programmed and tested at dallas to insure that no two devices are alike. the serial number can be used to electronically identify a system for purposes such as establishment of a network node address or for main- tenance tracking. blocks of available numbers from dal- las semiconductor can be reserved by the customer. the serialized rtc's also incorporate power control cir- cuitry which allows the system to be powered on via an external stimulus, such as a keyboard or by a time and date (wake up) alarm. the pwr output pin can be trig- gered by one or either of these events, and can be used to turn on an external power supply. the pwr pin is un- der software control, so that when a task is complete, the system power can then be shut down. the ds1689/DS1693 incorporates a power on elapsed time counter, a power on cycle counter, and a battery powered continuous counter. these three counters provide valuable information for maintenance and war- ranty requirements. automatic backup and write protection for an external sram is provided through the v cco and ceo pins. the lithium energy source used to permanently power the real time clock is also used to retain ram data in the absence of v cc power through the v cco pin. the chip enable out- put to ram (ceo ) is controlled during power transients to prevent data corruption. the ds1689 is a clock/calendar chip with the features described above. an external crystal and battery are the only components required to maintain timeofday and memory status in the absence of power. the DS1693 incorporates the ds1689 chip, a 32.768 khz crystal, and a lithium battery in a complete, selfcon- tained timekeeping module. the entire unit is fully tested at dallas semiconductor such that a minimum of 10 years of timekeeping and data retention in the absence of v cc is guaranteed. operation the block diagram in figure 1 shows the pin connec- tions with the major internal functions of the ds1689/DS1693. the following paragraphs describe the function of each pin. signal descriptions gnd, v cci - dc power is provided to the device on these pins. v cci is the +3 volt or +5 volt input. five volt operation is selected when the psel pin is at a logic 1. if psel is floated or at a logic 0, the device will be in auto- sense mode and will determine the correct operating voltage based on the v cci voltage level. psel (power select input) this pin selects whether 3 volt operation or 5 volt operation will be used. when psel is a logic 1, 5 volt operation is selected. when psel is a logic 0 or is floated, the device will be in auto- sense mode and will determine the correct mode of operation based on the voltage on v cci . v cco (external sram power supply output) this pin will be internally connected to v cci when v cci is within nominal limits. however, during power fail, v cco will be internally connected to the v bat or v baux (whichever is larger). for 5 volt operation, switch over from v cci to the backup supply occurs when v cci drops below the larger of v bat and v baux . for 3 volt opera- tion, switch over from v cci to the backup supply occurs at v pf if v pf is less than v bat and v baux . if v pf is greater than v bat and v baux , the switch from v cci to the backup supply occurs when v cci drops below the larger of v bat and v baux . ds1689/DS1693 030598 3/30 ds1689/DS1693 block diagram figure 1 osc v cc buffer enable periodic interrupt/square wave selector square wave out sqw irq double buffered registers a, b, c, d clock, calendar, and alarm bcd/binary increment clock/ calendar update bus interface ale rd wr ad0-ad7 x1 x2 v baux v cci cs pok + +3v v bat power control logic ks pwr cs select user ram 114 bytes ram clear logic rclr extended control/status registers 64 bit serial number century counter date alarm 64 8 64 control v bat elapsed time counter power cycle counter v cc elapsed time counter v cc level detect power switch and write protect psel 64bit customer specific rom or serial number v cco cei ceo ds1689/DS1693 030598 4/30 sqw (square wave output) the sqw pin can out- put a signal from one of 13 taps provided by the 15 inter- nal divider stages of the real time clock. the frequency of the sqw pin can be changed by programming regis- ter a as shown in table 2. the sqw signal can be turned on and off using the sqwe bit in register b. a 32 khz sqw signal is output when sqwe=1, the enable 32 khz (e32k) bit in extended register 04bh is a logic one, and v cc is above v pf . a 32 khz square wave is also available when v cc is less than v pf if e32k=1, abe=1, and voltage is applied to v baux. ad0ad7 (multiplexed bidirectional address/data bus) multiplexed buses save pins because address information and data information time share the same signal paths. the addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. address/data multiplexing does not slow the ac- cess time of the ds1689 since the bus change from ad- dress to data occurs during the internal ram access time. addresses must be valid prior to the latter portion of ale, at which time the ds1689/DS1693 latches the address. valid write data must be present and held stable during the latter portion of the wr pulse. in a read cycle the ds1689/DS1693 outputs 8 bits of data during the latter portion of the rd pulse. the read cycle is ter- minated and the bus returns to a high impedance state as rd transitions high. the address/data bus also serves as a bidirectional data path for the external ex- tended ram. ale (rtc address strobe input; active high) a pulse on the address strobe pin serves to demultiplex the bus. the falling edge of ale causes the rtc ad- dress to be latched within the ds1689/DS1693. rd (rtc read input; active low) rd identifies the time period when the ds1689/DS1693 drives the bus with rtc read data. the rd signal is an enable signal for the output buffers of the clock. wr (rtc write input; active low) the wr signal is an active low signal. the wr signal defines the time pe- riod during which data is written to the addressed regis- ter. cs (rtc chip select input; active low) the chip select signal must be asserted low during a bus cycle for the rtc portion of the ds1689/DS1693 to be ac- cessed. cs must be kept in the active state during rd and wr timing. bus cycles which take place with ale asserted but without asserting cs will latch addresses. however, no data transfer will occur. irq (interrupt request output; open drain, active low) the irq pin is an active low output of the ds1689/DS1693 that can be tied to the interrupt input of a processor. the irq output remains low as long as the status bit causing the interrupt is present and the corre- sponding interrupt-enable bit is set. to clear the irq pin, the application software must clear all enabled flag bits contributing to irq's active state. when no interrupt conditions are present, the irq level is in the high impedance state. multiple interrupting de- vices can be connected to an irq bus. the irq pin is an open drain output and requires an external pull-up re- sistor. cei (ram chip enable input; active low) cei should be driven low to enable the external ram. ceo (ram chip enable output; active low) when power is valid, ceo will equal cei . when power is not valid, ceo will be driven high regardless of cei . pwr (power on output; open drain, active low) the pwr pin is intended for use as an on/off control for the system power. with v cc voltage removed from the ds1689/DS1693, pwr may be automatically activated from a kickstart input via the ks pin or from a wake up interrupt. once the system is powered on, the state of pwr can be controlled via bits in the dallas registers. ks (kickstart input; active low) when v cc is re- moved from the ds1689/DS1693, the system can be powered on in response to an active low transition on the ks pin, as might be generated from a key closure. v baux must be present and auxiliary battery enable bit (abe) must be set to 1 if the kickstart function is used, and the ks pin must be pulled up to the v baux supply. while v cc is applied, the ks pin can be used as an inter- rupt input. rclr (ram clear input; active low) if enabled by software, taking rclr low will result in the clearing of the 114 bytes of user ram. when enabled, rclr can be activated whether or not v cc is present. v baux auxiliary battery input required for kickstart and wake up features. this input also supports clock/ calendar and external nvram if v bat is at lower volt- age or is not present. a standard +3 volt lithium cell or ds1689/DS1693 030598 5/30 other energy source can be used. battery voltage must be held between +2.5 and +3.7 volts for proper operation. if v baux is not going to be used it should be grounded and auxiliary battery enable bit bank 1, register 4bh, should=0. ds1689 only x1, x2 connections for a standard 32.768 khz quartz crystal. for greatest accuracy, the ds1689 must be used with a crystal that has a specified load capacitance of either 6 pf or 12.5 pf. the crystal select (cs) bit in extended control register 4b is used to select opera- tion with a 6 pf or 12.5 pf crystal. the crystal is attached directly to the x1 and x2 pins. there is no need for external capacitors or resistors. note: x1 and x2 are very high impedance nodes. it is recommended that they and the crystal by guardringed with ground and that high frequency signals be kept away from the crystal area. for more information on crystal selection and crystal layout considerations, please consult application note 58, acrystal considerations with dallas real time clockso. the ds1689 can also be driven by an external 32.768 khz oscillator. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated. v bat battery input for any standard 3 volt lithium cell or other energy source. battery voltage must be held be- tween 2.5 and 3.7 volts for proper operation. powerdown/powerup considerations the realtime clock function will continue to operate and all of the ram, time, calendar, and alarm memory loca- tions remain nonvolatile regardless of the level of the v cci input. when v cci is applied to the ds1689/DS1693 and reaches a level of greater than v pf (power fail trip point), the device becomes accessi- ble after t rec , provided that the oscillator is running and the oscillator countdown chain is not in reset (see regis- ter a). this time period allows the system to stabilize af- ter power is applied. when psel is floating or logic 0, the ds1689 is in auto- sense mode and 3 volt or 5 volt operation is determined based on the voltage on v cci . selection of 5 volt opera- tion is automatically invoked when v cci rises above 4.5 volts for a minimum of t rec . however, 3 volt operation is automatically selected if v cci does not rise above the level of 4.25 volts. selection of the power supply input levels requires 150 ms of input stability before operation can commence. when 5 volt operation is selected, the device is fully accessible and data can be written and read only when v cci is greater than 4.5 volts. when v cci is below 4.5 volts, read and writes are inhibited. however, the time- keeping function continues unaffected by the lower input voltage. as v cc falls below the greater of v bat and v baux , the ram and timekeeper are switched over to a lithium battery connected either to the v bat pin or v baux pin. when 3 volt operation is selected and applied within normal limits, the device is fully accessible and data can be written or read. when v cci falls below v pf , access to the device is inhibited. if v pf is less than v bat and v baux , the power supply is switched from v cci to the backup supply (the greater of v bat and v baux ) when v cci drops below v pf . if v pf is greater than v bat and v baux , the power supply is switched from v cci to the backup supply when v cci drops below the larger of v bat and v baux . when v cc falls below v pf , the chip is writeprotected. with the possible exception of the ks , pwr , and sqw pins, all inputs are ignored and all outputs are in a high impedance state. rtc address map the address map for the rtc registers of the ds1689/DS1693 is shown in figure 2. the address map consists of the 14 clock/calendar registers. ten registers contain the time, calendar, and alarm data, and four bytes are used for control and status. all regis- ters can be directly written or read except for the follow- ing: 1. registers c and d are readonly. 2. bit 7 of register a is readonly. 3. the high order bit of the seconds byte is readonly. ds1689/DS1693 030598 6/30 ds1689 real time clock address map figure 2 0 00h 13 14 0dh 0eh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 seconds seconds alarm minutes minutes alarm hours hours alarm day of the week day of the month month year register a register b register c register d binary or bcd inputs 07fh 127 clock/ calendar 14 bytes bank 0, 63 64 03fh 040h bank 1 registers, ram 50 bytes user ram time, calendar and alarm locations the time and calendar information is obtained by read- ing the appropriate register bytes shown in table 1. the time, calendar, and alarm are set or initialized by writing the appropriate register bytes. the contents of the time, calendar, and alarm registers can be either binary or binarycoded decimal (bcd) format. table 1 shows the binary and bcd formats of the twelve time, calendar, and alarm locations that reside in both bank 0 and in bank 1, plus the two extended registers that reside in bank 1 only (bank 0 and bank 1 switching will be ex- plained later in this text). before writing the internal time, calendar, and alarm reg- isters, the set bit in register b should be written to a logic one to prevent updates from occurring while ac- cess is being attempted. also at this time, the data for- mat (binary or bcd), should be set via the data mode bit (dm) of register b. all time, calendar, and alarm regis- ters must use the same data mode. the set bit in regis- ter b should be cleared after the data mode bit has been written to allow the real-time clock to update the time and calendar bytes. once initialized, the real-time clock makes all updates in the selected mode. the data mode cannot be changed without reinitializing the ten data bytes. the 24/12 bit cannot be changed without reinitializing the hour loca- tions. when the 12hour format is selected, the high order bit of the hours byte represents pm when it is a log- ic one. the time, calendar, and alarm bytes are always accessible because they are double buffered. once per second the ten bytes are advanced by one second and checked for an alarm condition. if a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. the probability of reading incorrect time and calendar data is low. several methods of avoiding any possible incorrect time and calendar reads are covered later in this text. the four alarm bytes can be used in two ways. first, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm inter- rupt is initiated at the specified time each day if the alarm enable bit is high . the second use condition is to insert a adon't careo state in one or more of the four alarm by- tes. the adon't careo code is any hexadecimal value from c0 to ff. the two most significant bits of each byte set the adon't careo condition when at logic 1. an alarm will be generated each hour when the adon't careo bits are set in the hours byte. similarly, an alarm is gener- ated every minute with adon't careo codes in the hours and minute alarm bytes. the adon't careo codes in all three alarm bytes create an interrupt every second. the three alarm bytes may be used in conjunction with the date alarm as described in the wakeup/kickstart sec- tion. the century counter will be discussed later in this text. ds1689/DS1693 030598 7/30 time, calendar and alarm data modes table 1 address function decimal range address location function decimal range binary data mode bcd data mode 00h seconds 059 003b 0059 01h seconds alarm 059 003b 0059 02h minutes 059 003b 0059 03h minutes alarm 059 003b 0059 04h hours 12hr. mode 112 010c am, 818c pm 0112 am, 8192 pm hours 24hour mode 023 0017 0023 05h hours alarm 12hr. mode 112 010c am, 818c pm 0112am, 8192 pm hours alarm 24hr. mode 023 0017 0023 06h day of week sunday=1 17 0107 0107 07h date of month 131 011f 0131 08h month 112 010c 0112 09h year 099 0063 0099 bank 1, 48h century 099 0063 0099 bank 1, 49h date alarm 131 011f 0131 control registers the four control registers; a, b, c, and d reside in both bank 0 and bank 1. these registers are accessible at all times, even during the update cycle. nonvolatile ram rtc the 114 general purpose nonvolatile ram bytes are not dedicated to any special function within the ds1689/DS1693. they can be used by the application program as nonvolatile memory and are fully available during the update cycle. this memory is directly acces- sible when bank 0 is selected. interrupt control the ds1689/DS1693 includes six separate, fully auto- matic sources of interrupt for a processor: 1. alarm interrupt 2. periodic interrupt 3. updateended interrupt 4. wake up interrupt 5. kickstart interrupt 6. ram clear interrupt the conditions which generate each of these indepen- dent interrupt conditions are described in greater detail elsewhere in this data sheet. this section describes the overall control of the interrupts. the application software can select which interrupts, if any, are to be used. there are a total of six bits including three bits in register b and three bits in extended reg- ister b which enable the interrupts. the extended regis- ter locations are described later. writing a logic 1 to an interrupt enable bit permits that interrupt to be initiated when the event occurs. a logic 0 in the interrupt enable bit prohibits the irq pin from being asserted from that interrupt condition. if an interrupt flag is already set when an interrupt is enabled, irq will immediately be set at an active level, even though the event initiating the interrupt condition may have occurred much earlier. as a result, there are cases where the software should clear these earlier generated interrupts before first en- abling new interrupts. when an interrupt event occurs, the relating flag bit is set to a logic 1 in register c or in extended register a. these flag bits are set regardless of the setting of the corresponding enable bit located either in register b or in extended register b. the flag bits can be used in a polling mode without enabling the corresponding en- able bits. ds1689/DS1693 030598 8/30 however, care should be taken when using the flag bits of register c as they are automatically cleared to 0 im- mediately after they are read. double latching is imple- mented on these bits so that bits which are set remain stable throughout the read cycle. all bits which were set are cleared when read and new interrupts which are pending during the read cycle are held until after the cycle is completed. one, two, or three bits can be set when reading register c. each utilized flag bit should be examined when read to ensure that no interrupts are lost. the flag bits in extended register a are not automati- cally cleared following a read. instead, each flag bit can be cleared to 0 only by writing 0 to that bit. when using the flag bits with fully enabled interrupts, the irq line will be driven low when an interrupt flag bit is set and its corresponding enable bit is also set. irq will be held low as long as at least one of the six possible interrupt sources has it s flag and enable bits both set. the irqf bit in register c is a 1 whenever the irq pin is being driv- en low as a result of one of the six possible active sources. therefore, determination that the ds1689/DS1693 initi- ated an interrupt is accomplished by reading register c and finding irqf=1. irqf will remain set until all enabled interrupt flag bits are cleared to 0. square wave output selection the sqw pin can be programmed to output a variety of frequencies divided down from the 32.768 khz crystal tied to x1 and x2. the square wave output is enabled and disabled via the sqwe bit in register b. if the square wave is enabled (sqwe=1), then the output fre- quency will be determined by the settings of the e32k bit in extended register b and by the rs3-0 bits in regis- ter a. if the e32k = 1, then a 32.768 khz square wave will be output on the sqw pin regardless of the settings of rs30. if e32k = 0, then the square wave output frequency is determined by the rs3-0 bits. these bits control a 1of15 decoder which selects one of thirteen taps that divide the 32.768 khz frequency. the rs30 bits es- tablish the sqw output frequency as shown in table 2. in addition, rs30 bits control the periodic interrupt selection as described below. if sqwe1, e32k=1, and the auxiliary battery enable bit (abe, bank 1; register 04bh) is enabled, and voltage is applied to v baux then the 32 khz square wave output signal will be output on the sqw pin in the absence of v cc . this facility is provided to clock external power management circuitry. if any of the above requirements are not met, no square wave output signal will be gener- ated on the sqw pin in the absence of v cc . a pattern of 01x in the dv2, dv1, and dv0, bits respec- tively, will turn the oscillator on and enable the count- down chain. note that this is different than the ds1287, which required a pattern of 010 in these bits. dv0 is now a adon't careo because it is used for selection between register banks 0 and 1. a pattern of 11x will turn the oscillator on, but the oscilla- tor's countdown chain will be held in reset, as it was in the ds1287. any other bit combination for dv2 and dv1 will keep the oscillator off. periodic interrupt selection the periodic interrupt will cause the irq pin to go to an active state from once every 500 ms to once every 122 m s. this function is separate from the alarm inter- rupt which can be output from once per second to once per day. the periodic interrupt rate is selected using the same rs30 bits in register a which select the square wave frequency (see table 2). changing the bits affects both the square wave frequency and the periodic inter- rupt output. however, each function has a separate en- able bit in register b. the sqwe bit controls the square wave output. similarly, the periodic interrupt is enabled by the pie bit in register b. the periodic interrupt can be used with software counters to measure inputs, create output intervals, or await the next needed soft- ware function. update cycle the serialized rtc executes an update cycle once per second regardless of the set bit in register b. when the set bit in register b is set to one, the user copy of the double buffered time, calendar, alarm and elapsed time byte is frozen and will not update as the time incre- ments. however, the time countdown chain continues to update the internal copy of the buffer. this feature al- lows the time to maintain accuracy independent of read- ing or writing the time, calendar, and alarm buffers and also guarantees that time and calendar information is consistent. the update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a adon't careo code is present in all three positions. ds1689/DS1693 030598 9/30 there are three methods that can handle access of the realtime clock that avoid any possibility of accessing inconsistent time and calendar data. the first method uses the update-ended interrupt. if enabled, an inter- rupt occurs after every up date cycle that indicates that over 999 ms are available to read valid time and date in- formation. if this interrupt is used, the irqf bit in regis- ter c should be cleared before leaving the interrupt routine. a second method uses the updateinprogress bit (uip) in register a to determine if the update cycle is in progress. the uip bit will pulse once per second. after the uip bit goes high, the update transfer occurs 244 m s later. if a low is read on the uip bit, the user has at least 244 m s before the time/calendar data will be changed. therefore, the user should avoid interrupt service rou- tines that would cause the time needed to read valid time/calendar data to exceed 244 m s. periodic interrupt rate and square wave output frequency table 2 ext. reg. b select bits register a t pi periodic sqw output e32k rs3 rs2 rs1 rs0 t pi periodic interrupt rate sqw output frequency 0 0 0 0 0 none none 0 0 0 0 1 3.90625 ms 256 hz 0 0 0 1 0 7.8125 ms 128 hz 0 0 0 1 1 122.070 m s 8.192 khz 0 0 1 0 0 244.141 m s 4.096 khz 0 0 1 0 1 488.281 m s 2.048 khz 0 0 1 1 0 976.5625 m s 1.024 khz 0 0 1 1 1 1.953125 ms 512 hz 0 1 0 0 0 3.90625 ms 256 hz 0 1 0 0 1 7.8125 ms 128 hz 0 1 0 1 0 15.625 ms 64 hz 0 1 0 1 1 31.25 ms 32 hz 0 1 1 0 0 62.5 ms 16 hz 0 1 1 0 1 125 ms 8 hz 0 1 1 1 0 250 ms 4 hz 0 1 1 1 1 500 ms 2 hz 1 x x x x * 32.768 khz *rs3-rs0 determine periodic interrupt rates as listed for e32k=0. the third method uses a periodic interrupt to determine if an update cycle is in progress. the uip bit in register a is set high between the setting of the pf bit in register c (see figure 3). periodic interrupts that occur at a rate of greater than t buc allow valid time and date informa- tion to be reached at each occurrence of the periodic in- terrupt. the reads should be complete within (t pi / 2+t buc ) to ensure that data is not read during the update cycle. ds1689/DS1693 030598 10/30 updateended and periodic interrupt relationship figure 3 ?? ?? ?? ?? ?? ?? t buc t pi/2 t pi/2 t pi uip bit in register a uf bit in register c pf bit in register c t pi = periodic interrupt time internal per table 1 t buc = delay time before update cycle = 244 m s register a msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uip dv2 dv1 dv0 rs3 rs2 rs1 rs0 uip the update in progress (uip) bit is a status flag that can be monitored. when the uip bit is a one, the update transfer will soon occur. when uip is a zero, the update transfer will not occur for at least 244 m s. the time, calendar, and alarm information in ram is fully available for access when the uip bit is zero. the uip bit is read only. writing the set bit in register b to a one inhibits any update transfer and clears the uip status bit. dv0, dv1, dv2 these bits are defined as follows: dv2 = countdown chain 1 resets countdown chain only if dv1=1 0 countdown chain enabled dv1 = oscillator enable 0 oscillator off 1 oscillator on dv0 = bank select 0 original bank 1 extended registers a pattern of 01x is the only combination of bits that will turn the oscillator on and allow the rtc to keep time. a pattern of 11x will enable the oscillator but holds the countdown chain in reset. the next update will occur at 500 ms after a pattern of 01x is written to dv2, dv1, and dv0. rs3, rs2, rs1, rs0 these four rateselection bits select one of the 13 taps on the 15stage divider or dis- able the divider output. the tap selected can be used to generate an output square wave (sqw pin) and/or a pe- riodic interrupt. the user can do one of the following enable the interrupt with the pie bit; enable the sqw output pin with the sqwe bit; enable both at the same time and the same rate; or enable neither. table 2 lists the periodic interrupt rates and the square wave frequencies that can be chosen with the rs bits. ds1689/DS1693 030598 11/30 register b msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set pie aie uie sqwe dm 24/12 dse set when the set bit is a zero, the update transfer functions normally by advancing the counts once per second. when the set bit is written to a one, any update transfer is inhibited and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. read cycles can be executed in a similar manner. set is a read/write bit that is not modi- fied by internal functions of the ds1689/DS1693. pie the periodic interrupt enable bit is a read/write bit which allows the periodic interrupt flag (pf) bit in reg- ister c to drive the irq pin low. when the pie bit is set to one, periodic interrupts are generated by driving the irq pin low at a rate specified by the rs3rs0 bits of register a. a zero in the pie bit blocks the irq output from being driven by a periodic interrupt, but the period- ic flag (pf) bit is still set at the periodic rate. pie is not modified by any internal ds1689/DS1693 functions. aie the alarm interrupt enable (aie) bit is a read/ write bit which, when set to a one, permits the alarm flag (af) bit in register c to assert irq . an alarm inter- rupt occurs for each second that the three time bytes equal the three alarm bytes including a don't care alarm code of binary 11xxxxxx. when the aie bit is set to zero, the af bit does not initiate the irq signal. the in- ternal functions of the ds1689/DS1693 do not affect the aie bit. uie the update ended interrupt enable (uie) bit is a read/write that enables the update end flag (uf) bit in register c to assert irq . the set bit going high clears the uie bit. sqwe when the square wave enable (sqwe) bit is set to a one, a square wave signal at the frequency set by the rateselection bits rs3 through rs0 and the e32k bit is driven out on the sqw pin. when the sqwe bit is set to zero, the sqw pin is held low. sqwe is a read/write bit. dm the data mode (dm) bit indicates whether time and calendar information is in binary or bcd format. the dm bit is set by the program to the appropriate for- mat and can be read as required. this bit is not modified by internal functions. a one in dm signifies binary data while a zero in dm specifies binary coded decimal (bcd) data. 24/12 the 24/12 control bit establishes the format of the hours byte. a one indicates the 24hour mode and a zero indicates the 12-hour mode. this bit is read/write. dse the daylight savings enable (dse) bit is a read/ write bit which enables two special updates when dse is set to one. on the first sunday in april the time incre- ments from 1:59:59 am to 3:00:00 am. on the last sunday in october when the time first reaches 1:59:59 am it changes to 1:00:00 am. these special updates do not occur when the dse bit is a zero. this bit is not af- fected by internal functions. register c msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irqf pf af uf 0 0 0 0 irqf the interrupt request flag (irqf) bit is set to a one when one or more of the following are true: pf = pie = 1 wf = wie = 1 af = aie = 1 kf = kse= 1 uf = uie = 1 rf = rie = 1 i.e., irqf = ( pf ? pie ) + ( af ? aie ) + ( uf ? uie ) + ( wf ? wie ) + ( kf ? kse ) + ( rf ? rie ) any time the irqf bit is a one, the irq pin is driven low. flag bits pf, af, and uf are cleared after register c is read by the program. pf the periodic interrupt flag (pf) is a readonly bit which is set to a one when an edge is detected on the selected tap of the divider chain. the rs3 through rs0 bits establish the periodic rate. pf is set to a one inde- pendent of the state of the pie bit. when both pf and pie are ones, the irq signal is active and will set the irqf bit. the pf bit is cleared by a software read of register c. af a one in the alarm interrupt flag (af) bit indicates that the current time has matched the alarm time. if the aie bit is also a one, the irq pin will go low and a one will appear in the irqf bit. a read of register c will clear af. ds1689/DS1693 030598 12/30 uf the update ended interrupt flag (uf) bit is set af- ter each update cycle. when the uie bit is set to one, the one in uf causes the irqf bit to be a one which will as- sert the irq pin. uf is cleared by reading register c. bit 0 through bit 3 these are unused bits of the status register c. these bits always read zero and can- not be written. register d msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vrt 0 0 0 0 0 0 0 vrt the valid ram and time (vrt) bit indicates the condition of the battery connected to the v bat pin or the battery connected to v baux , whichever is at a higher voltage. this bit is not writable and should always be a one when read. if a zero is ever present, an exhausted lithium energy source is indicated and both the contents of the rtc data and ram data are questionable. bit 6 through bit 0 the remaining bits of register d are not usable. they cannot be written and, when read, they will always read zero. extended functions the extended functions provided by the ds1689/DS1693 that are new to the ramified rtc family are accessed via a software controlled bank switching scheme, as illustrated in figure 4. in bank 0, the clock/calendar registers and 50 bytes of user ram are in the same locations as for the ds1287. as a result, existing routines implemented within bios, dos, or ap- plication software packages can gain access to the ds1689/DS1693 clock registers with no changes. also in bank 0, an extra 64 bytes of ram are provided at ad- dresses just above the original locations for a total of 114 directly addressable bytes of user ram. when bank 1 is selected, the clock/calendar registers and the original 50 bytes of user ram still appear as bank 0. however, the dallas registers which provide control and status for the extended functions will be ac- cessed in place of the additional 64 bytes of user ram. the major extended functions controlled by the dallas registers are listed below: 1. silicon revision byte 2. serial number 3. eight byte customer specific rom or serial number 4. century counter 5. auxiliary battery control/status 6. wake up 7. kickstart 8. ram clear control/status 9. v cc powered elapsed time counter 10. v bat powered elapsed time counter 11. power on cycle counter the bank selection is controlled by the state of the dv0 bit in register a. to access bank 0 the dv0 bit should be written to a 0. to access bank 1, dv0 should be written to a 1. register locations designated as reserved in the bank 1 map are reserved for future use by dallas semi- conductor. bits in these locations cannot be written and will return a 0 if read. ds1689/DS1693 030598 13/30 ds1689/DS1693 extended register bank definition figure 4 v cc elapsed time counter v cc elapsed time counter v cc elapsed time counter v cc elapsed time counter v bat elapsed time counter v bat elapsed time counter v bat elapsed time counter v bat elapsed time counter power cycle counter power cycle counter 00 od 0e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 7f dv0 = 1 00 od 0e 3f 7f dv0 = 0 bank 0 bank 1 timekeeping and control 50 bytesuser ram 64 bytesuser ram timekeeping and control 50 bytesuser ram model byte 1st byte serial # 2nd byte serial # 3rd byte serial # 4th byte serial # 5th byte serial # 6th byte serial # crc byte century byte date alarm extended control reg 4a extended control reg 4b reserved reserved reserved reserved reserved reserved reserved reserved msb lsb msb lsb 55 56 57 58 59 5a 5b 5c 5d 60 67 8byte customer specific reserved rom or serial number 5e 5f reserved ds1689/DS1693 030598 14/30 silicon serial number/customer specific rom a total of 128 bits are available for use as serial number/ rom. these bits may be used as a 128bit serial num- ber or as a unique 64bit serial number and 64bit cus- tomer specific serial number or rom. the unique 64bit serial number is located in bank 1 registers 40h-47h. this serial number is divided into three parts. the first byte in register 40h contains a model number to identify the device type and revision of the ds1689/DS1693. registers 41h46h contain a unique binary number. register 47h contains a crc byte used to validate the data in registers 40h46h. the method used to create the crc byte is proprietary to dallas semiconductor, but can be made available if required. typical applications should consider this byte simply as part of the overall unique serial number. all 8 bytes of the serial number are read only registers. the ds1689/DS1693 is manufactured such that no two devices will contain an identical number in locations 41h47h. blocks of numbers for these locations can be reserved by the customer. contact dallas semiconduc- tor for special ordering information for ds1689/DS1693 with reserved blocks of serial numbers. as already mentioned, another 64 bits are available for use as an additional serial number or customer specific rom. these 64 bits are located in bank 1 registers 60h67h. century counter a register has been added in bank 1, location 48h, to keep track of centuries. the value is read in either binary or bcd according to the setting of the dm bit. auxiliary battery the v baux input is provided to supply power from an auxiliary battery for the ds1689/DS1693 kickstart, wake up, and sqw output features in the absence of v cc . this power source must be available in order to use these auxiliary features when no v cc is applied to the device. the auxiliary battery enable (abe; bank 1, register 04bh) bit in extended control register b is used to turn on and off the auxiliary battery for the above functions in the absence of v cc . when set to a 1, v baux battery power is enabled, and when cleared to 0, v baux battery power is disabled to these functions. in the ds1689/DS1693, this auxiliary battery may be used as the primary backup power source for maintain- ing the clock/calendar, user ram, and extended exter- nal ram functions. this occurs if the v bat pin is at a lower voltage than v baux . if the ds1689 is to be backedup using a single battery with the auxiliary fea- tures enabled, then v baux should be used and con- nected to v bat . if v baux is not to be used, it should be grounded and abe should be cleared to 0. wake up/kickstart the ds1689/DS1693 incorporates a wake up feature which can power the system on at a predetermined date through activation of the pwr output pin. in addi- tion, the kickstart feature can allow the system to be powered up in response to a low going transition on the ks pin, without operating voltage applied to the v cc pin. as a result, system power may be applied upon such events as a key closure, or modem ring detect signal. in order to use either the wake up or the kickstart features, the ds1689/DS1693 must have an auxiliary battery connected to the v baux pin and the oscillator must be running and the countdown chain must not be in reset (register a dv2, dv1, dv0 = 01x). if dv2, dv1, and dv0 are not in this required state, the pwr pin will not be driven low in response to a kickstart or wakeup condi- tion, while in battery-backed mode. the wake up feature is controlled through the wake up interrupt enable bit in extended control register b (wie, bank 1, 04bh). setting wie to 1 enables the wake up feature, clearing wie to 0 disables it. similarly, the kick- start feature is controlled through the kickstart interrupt enable bit in extended control register b (kse, bank 1, 04bh). a wake up sequence will occur as follows: when wake up is enabled via wie = 1 while the system is powered down (no v cc voltage), the clock/calendar will monitor the current date for a match condition with the date alarm register (bank 1, register 049h). in conjunction with the date alarm register, the hours, minutes, and se- conds alarm bytes in the clock/calendar register map (bank 0, registers 05h, 03h, and 01h) are also moni- tored. as a result, a wake up will occur at the date and time specified by the date, hours, minutes, and seconds alarm register values. this additional alarm will occur regardless of the programming of the aie bit (bank 0, register b, 0bh). when the match condition occurs, the pwr pin will automatically be driven low. this output can be used to turn on the main system power supply ds1689/DS1693 030598 15/30 which provides v cc voltage to the ds1689/DS1693 as well as the other major components in the system. also at this time, the wake up flag (wf, bank 1, register 04ah) will be set, indicating that a wake up condition has occurred. a kickstart sequence will occur when kickstarting is en- abled via kse = 1. while the system is powered down, the ks input pin will be monitored for a low going transi- tion of minimum pulse width t kspw . when such a transi- tion is detected, the pwr line will be pulled low, as it is for a wake up condition. also at this time, the kickstart flag (kf, bank 1, register 04ah) will be set, indicating that a kickstart condition has occurred. the timing associated with both the wake up and kick- starting sequences is illustrated in the wake up / kick- start timing diagram in the electrical specifications section of this data sheet. the timing associated with these functions is divided into 5 intervals, labeled 1-5 on the diagram. the occurrence of either a kickstart or wake up condi- tion will cause the pwr pin to be driven low, as de- scribed above. during interval 1, if the supply voltage on the ds1689/DS1693 v cc pin rises above the 3 volt power fail level before the power on timeout period (t poto ) expires, then pwr will remain at the active low level. if v cc does not rise above the 3 volt power fail voltage in this time, then the pwr output pin will be turned off and will return to its high impedance level. in this event, the irq pin will also remain tristated. the interrupt flag bit (either wf or kf) associated with the attempted power on sequence will remain set until cleared by software during a subsequent system power on. if v cc is applied within the timeout period, then the sys- tem power on sequence will continue as shown in inter- vals 25 in the timing diagram. during interval 2, pwr will remain active and irq will be driven to its active low level, indicating that either wf or kf was set in initiating the power on. in the diagram ks is assumed to be pulled up to the v baux supply. also at this time, the pab bit will be automatically cleared to 0 in response to a success- ful power on. the pwr line will remain active as long as the pab remains cleared to 0. at the beginning of interval 3, the system processor has begun code execution and clears the interrupt condition of wf and/or kf by writing zeroes to both of these con- trol bits. as long as no other interrupt within the ds1689/DS1693 is pending, the irq line will be taken inactive once these bits are reset. execution of the ap- plication software may proceed. during this time, both the wake up and kickstart functions may be used to gen- erate status and interrupts. wf will be set in response to a date, hours, and minutes match condition. kf will be set in response to a low going transition on ks . if the associated interrupt enable bit is set (wie and/or kse) then the irq line will driven active low in response to en- abled event. in addition, the other possible interrupt sources within the ds1689/DS1693 may cause irq to be driven low. while system power is applied, the on chip logic will always attempt to drive the pwr pin active in response to the enabled kickstart or wake up condi- tion. this is true even if pwr was previously inactive as the result of power being applied by some means other than wake up or kickstart. the system may be powered down under software con- trol by setting the pab bit to a logic 1. this causes the open-drain pwr pin to be placed in a high impedance state, as shown at the beginning of interval 4 in the tim- ing diagram. as v cc voltage decays, the irq output pin will be placed in a high impedance state when v cc goes below v pf . if the system is to be again powered on in response to a wake up or kickstart, then the both the wf and kf flags should be cleared and wie and/or kse should be enabled prior to setting the pab bit. during interval 5, the system is fully powered down. battery backup of the clock calendar and nonvolatile ram is in effect, pwr and irq are tri-stated, and moni- toring of wake up and kickstart takes place. ram clear the ds1689/DS1693 provides a ram clear function for the 114 bytes of user ram. when enabled, this function can be performed regardless of the condition of the v cc pin. ds1689/DS1693 030598 16/30 the ram clear function is enabled or disabled via the ram clear enable bit (rce; bank 1, register 04bh). when this bit is set to a logic 1, the 114 bytes of user ram will be cleared (all bits set to 1) when an active low transition is sensed on the rclr pin. this action will have no effect on either the clock/calendar settings or upon the contents of the external extended ram. the ram clear flag (rf, bank 1, register 04bh) will be set when the ram clear operation has been completed. if v cc is present at the time of the ram clear and rie=1, the irq line will also be driven low upon completion. the interrupt condition can be cleared by writing a zero to the rf bit. the irq line will then return to its inactive high level provided there are no other pending inter- rupts. once the rclr pin is activated, all read/write ac- cesses are locked out for a minimum recover time, spe- cified as t rec in the electrical characteristics section. when rce is cleared to zero, the ram clear function is disabled. the state of the rclr pin will have no effect on the contents of the user ram, and transitions on the rclr pin have no effect on rf. extended control registers two extended control registers are provided to supply controls and status information for the extended fea- tures offered by the ds1689/DS1693. these are desig- nated as extended control registers a and b and are lo- cated in register bank 1, locations 04ah and 04bh, respectively. the functions of the bits within these regis- ters are described as follows. extended control register 4a msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vrt2 incr * * pab rf wf kf vrt2 this status bit gives the condition of the auxilia- ry battery. it is set to a logic 1 condition when the exter- nal lithium battery is connected to the v baux . if this bit is read as a logic 0, the external battery should be re- placed. incr increment in progress status bit. this bit is set to a 1 when an increment to the time/date registers is in progress and the alarm checks are being made. incr will be set to a 1 at 122 m s before the update cycle starts and will be cleared to 0 at the end of each update cycle. pab power active bar control bit. when this bit is 0, the pwr pin is in the active low state. this bit can be written to a logic 1 or 0 by the user. if either wf and wie = 1 or kf and kse = 1, the pab bit will be cleared to 0. rf ram clear flag. this bit will be set to a logic 1 when a high to low transition occurs on the rclr input if rce=1. the rf bit is cleared by writing it to a logic 0. this bit can also be written to a logic 1 to force an inter- rupt condition. wf wake up alarm flag this bit is set to 1 when a wake up alarm condition occurs or when the user writes it to a 1. wf is cleared by writing it to a 0. kf kickstart flag this bit is set to a 1 when a kick- start condition occurs or when the user writes it to a 1. this bit is cleared by writing it to a logic 0. extended control register 4b msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 abe e32k cs rce prs rie wie kse abe auxiliary battery enable. this bit when written to a logic 1 will enable the v baux pin for extended func- tions. e32k enable 32,768 output. this bit when written to a logic 1 will enable the 32,768 hz oscillator frequency to be output on the sqw pin provided sqwe=1. cs crystal select bit. when cs is set to a 0, the oscil- lator is configured for operation with a crystal that has a 6 pf specified load capacitance. when cs=1, the oscil- lator is configured for a 12.5 pf crystal. rce ram clear enable bit. when set to a 1, this bit enables a low level on pin 4 (rclr ) to clear all 114 bytes of user ram. when rce = 0, the ram clear function is disabled. prs pab reset select bit. when set to a 0 the pwr pin will be set hiz when the ds1689 goes into power fail. when set to a 1, the pwr pin will remain active upon entering power fail. ds1689/DS1693 030598 17/30 rie ram clear interrupt enable. when rie is set to a 1, the irq pin will be driven low when a ram clear func- tion is completed. wie wake up alarm interrupt enable. when v cc volt- age is absent and wie is set to a 1, the pwr pin will be driven active low when a wake up condition occurs, causing the wf bit to be set to 1. when v cc is then ap- plied, the irq pin will also be driven low. if wie is set while system power is applied, both irq and pwr will be driven low in response to wf being set to 1. when wie is cleared to a 0, the wf bit will have no effect on the pwr or irq pins. kse kickstart interrupt enable. when v cc voltage is absent and kse is set to a 1, the pwr pin will be driven active low when a kickstart condition occurs (ks pulsed low), causing the kf bit to be set to 1. when v cc is then applied, the irq pin will also be driven low. if kse is set to 1 while system power is applied, both irq and pwr will be driven low in response to kf being set to 1. when kse is cleared to a 0, the kf bit will have no effect on the pwr or irq pins. * reserved bits. these bits are reserved for future use by dallas semiconductor. they can be read and writ- ten, but have no effect on operation. elapsed time counters the ds1689/DS1693 has two 32 bit elapsed time counters, which reside in bank 1 of the rtc registers. to access these counters the dv0 bit in register a must first be set to a logical 1. the v cc powered elapsed time counter resides in regis- ter 54h through 57h. the lsb of this counter resides in register 54 and the msb is in 57h. the v cc powered elapsed time counter runs only while the v cci input is within nominal limits. the elapsed time counter is a binary counter that records the number of seconds that have elapsed. the counter can be read or written at the users discretion. the v bat powered elapsed time counter resides in register 58h through 5bh. the lsb of this counter resides in register 58 and the msb is in 5bh. the v bat powered elapsed time counter runs continual- ly as long as the v bat or v baux pin is within nominal lim- its regardless of the condition of v cci . the number of seconds that have elapsed are recorded in a binary counter and the counter may be read or written at the user's discretion. in a typical application the v bat powered elapsed time counter can be used to record the length of time that has elapsed from which the equipment which contains the device was first put into service. the v cc powered counter can then be used to record the length of time that v cc power is applied. these functions can be par- ticularly useful for warranty and maintenance informa- tion. in addition, battery life can be predicted based on known loading factors. however, it is worth noting that a properly selected battery should power the ds1689/DS1693 and external ram for the useful life of most equipment. power cycle counter the ds1689/DS1693 has a 16 bit power cycle counter that resides in register 5c and 5d of bank 1. the lsb of this counter resides in 5c and the msb is in 5d. this binary counter is incremented by 1 count each time v cci power is applied within nominal limits. this counter can be read or written at the user's discretion. ds1689/DS1693 030598 18/30 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature ds1689 and ds1689s 40 c to +85 c operating temperature DS1693 0 c to 70 c storage temperature 40 c to +70 c soldering temperature 260 c for 10 seconds (see note 18) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes power supply voltage 5 volt operation v cci 4.5 5.0 5.5 v 1 power supply voltage 3 volt operation v cci 2.7 3.0 4.0 v 1 input logic 1 v ih 2.2 v cc +0.3 v 1 input logic 0 v il -0.3 0.6 v 1 battery voltage v bat 2.5 3.7 v 1 auxiliary battery voltage v baux 2.5 3.7 v 1 dc electrical characteristics (0 c to 70 c; v cc =4.5v to 5.5 v) parameter symbol min typ max units notes average v cc power supply current i cc1 7 15 ma 2, 3 cmos standby current (cs =v cc -0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il 1 +1 m a cei input leakage i cei 200 +1 m a 15 psel input leakage i psel 1 +200 m a 16 output leakage current i ol -1 +1 m a 8 output logic 1 voltage (i out = 1.0 ma) v oh 2.4 v output logic 0 voltage (i out = +2.1 ma) v ol 0.4 v output voltage v cco1 v cc -0.3 v 4 output current i cco1 85 ma 4 power fail trip point v pf 4.25 4.37 4.5 v 5 battery switch voltage v sw v bat , v baux v output voltage v cco2 v bat -0.3 v 6 ds1689/DS1693 030598 19/30 dc electrical characteristics (cont'd) (0 c to 70 c; v cc =4.5v to 5.5 v) output current i cco2 100 m a 6 battery leakage osc on i bat1 500 1000 na battery leakage osc off i bat2 50 150 na 17 i/o leakage i lo 1 +1 m a 7 pwr output @ 0.4v i olpwr 10.0 ma 1 cei to ceo impedance z ce 60 w 12 dc electrical characteristics (0 c to 70 c; v cc =2.7v to 4.0 v) parameter symbol min typ max units notes average v cc power supply current i cc1 5 10 ma 2, 3 cmos standby current (cs =v cc 0.2v) i cc2 0.5 2 ma 2, 3 input leakage current (any input) i il 1 +1 m a cei input leakage i cei 160 +1 m a 15 psel input leakage i psel +1 160 m a 16 output leakage current i ol +160 1 m a 8 output logic 1 voltage @ 0.4 ma v oh 2.4 v output logic 0 voltage @ 0.8 ma v ol 0.4 v output voltage v cco1 v cc -0.3 v 4 output current i cco1 50 ma 4 power fail trip point v pf 2.5 2.6 2.7 v 5 output voltage v cco2 v bat -0.3 v 6 output current i cco2 100 m a 6 battery leakage osc on i bat1 500 1000 na battery leakage osc off i bat2 50 150 na 17 i/o leakage i lo 1 +1 m a 7 pwr output @ 0.4v i olpwr 4 ma 1 cei to ceo impedance z ce 120 w 12 ds1689/DS1693 030598 20/30 rtc ac timing characteristics (0 c to 70 c; v cc = 2.7v to 4.0v) parameter symbol min typ max units notes cycle time t cyc 915 dc ns pulse width, rd /wr low pw rwl 375 ns pulse width, rd /wr high pw rwh 450 ns input rise and fall time t r , t f 30 ns chip select setup time before wr , or rd t cs 75 ns chip select hold time t ch 0 ns read data hold time t dhr 10 120 ns write data hold time t dhw 0 ns muxed address valid time to ale fall t asl 90 ns muxed address hold time from ale fall t ahl 30 ns rd or wr high setup to ale rise t asd 30 ns pulse width ale high pw ash 180 ns ale low setup to rd or wr fall t ased 120 ns output data delay time from rd t ddr 20 370 ns 9 data setup time t dsw 180 ns irq release from rd t ird 2 m s cei to ceo delay t ced 20 ns ds1689/DS1693 030598 21/30 ds1689/DS1693 bus timing for read cycle to rtc t cyc pw rwl pw ash t asd t ased t asd pw rwh t cs t ch t dhr t ahl t asl ale wr rd cs ad0ad7 t ddr irq t ird t cyc pw rwl pw ash t asd t ased t asd pw rwh t cs t dsw t ch t dhw t ahl t asl ale wr rd cs ad0ad7 ds1689/DS1693 030598 22/30 rtc ac timing characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol min typ max units notes cycle time t cyc 305 dc ns pulse width, rd /wr low pw rwl 125 ns pulse width, rd /wr high pw rwh 150 ns input rise and fall time t r , t f 30 ns chip select setup time before wr , or rd t cs 20 ns chip select hold time t ch 0 ns read data hold time t dhr 10 80 ns write data hold time t dhw 0 ns muxed address valid time to ale fall t asl 30 ns muxed address hold time from ale fall t ahl 10 ns rd or wr high setup to ale rise t asd 25 ns pulse width ale high pw ash 60 ns ale low setup to rd or wr fall t ased 40 ns output data delay time from rd t ddr 20 120 ns 9 data setup time t dsw 100 ns irq release from rd t ird 2 m s cei to ceo delay t ced 10 ns ds1689/DS1693 bus timing for write cycle to rtc and rtc registers ds1689/DS1693 030598 23/30 powerup condition 3 volt operation power fail cs v cc v ih t rec 3.0v 2.7v 2.5v t r powerdown condition 3 volt operation v ih t pf t f 3.0v 2.7v 2.5v power fail cs v cc ds1689/DS1693 030598 24/30 powerup condition 5.0 volt operation power fail cs v cc v ih t rec 4.5v 4.25v 4.0v t r powerdown condition 5.0 volt operation v ih t pf t f t fb v bat 4.5v 4.25v 4.0v power fail cs v cc ds1689/DS1693 030598 25/30 powerup powerdown timing 5 volt operation (t a = 25 c) parameter symbol min typ max units notes cs high to power fail t pf 0 ns recovery at power up t rec 150 ms v cc slew rate powerdown t f 4.0 < v cc < 4.5v 300 m s v cc slew rate powerdown t fb 3.0 < v cc < 4.0v 10 m s v cc slew rate powerup t r 4.5v> v cc > 4.0v 0 m s expected data retention t dr 10 years 13, 14 powerup powerdown timing 3 volt operation (t a = 25 c) parameter symbol min typ max units notes cs high to power fail t pf 0 ns recovery at powerup t rec 150 ms v cc slew rate powerdown t f 2.5 < v cc < 3.0v 300 m s v cc slew rate powerup t r 3.0v> v cc > 2.5v 0 m s expected data retention t dr 10 years 13, 14 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery back-up mode. capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 12 pf output capacitance c out 12 pf wake up/kickstart timing (t a = 25 c) parameter symbol min typ max units notes kickstart input pulse width t kspw 2 m s wake up/kickstart power on timeout t poto 2 seconds 10 ds1689/DS1693 030598 26/30 wake up/kickstart timing 1 2 3 4 5 irq pwr ks wf/kf (internal) 0v v bat v pf v pf >v bat t potp t kspw v ih hi-z v il v ih hi-z v il v ih v il 0v v pf v bat v pf ds1689/DS1693 030598 28/30 ds1689 28pin dip 1 c a b d h j k g e f dim min max 28pin pkg a in. 1.445 1.470 mm 36.70 37.34 b in. 0.530 0.550 mm 13.46 13.97 c in. 0.140 0.160 mm 3.56 4.06 d in. 0.600 0.625 mm 15.24 15.88 e in. 0.015 0.040 mm 0.38 1.02 f in. 0.120 0.145 mm 3.05 3.68 g in. 0.090 0.110 mm 2.29 2.79 h in. 0.625 0.675 mm 15.88 17.15 j in. 0.008 0.012 mm 0.20 0.30 k in. 0.015 0.022 mm 0.38 0.56 ds1689/DS1693 030598 29/30 ds1689s 28pin soic h b j k g c e a f d 08 deg. typ. dim min max 28pin pkg a in. 0.706 0.728 mm 17.93 18.49 b in. 0.338 0.350 mm 8.58 8.89 c in. 0.086 0.110 mm 2.18 2.79 d in. 0.020 0.050 mm 0.58 1.27 e in. 0.002 0.014 mm 0.05 0.36 f in. 0.090 0.124 mm 2.29 3.15 g in. mm h in. 0.460 0.480 mm 11.68 12.19 j in. 0.006 0.013 mm 0.15 0.33 k in. 0.014 0.020 mm 0.36 0.51 0.050 bsc 1.27 ds1689/DS1693 030598 30/30 DS1693 28pin 740 mil module a 28 114 15 c e f k d g b h j dim min max a in. mm b in. mm c in. mm d in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 1.520 38.61 1.540 39.12 0.695 17.65 0.740 18.80 0.350 8.89 0.375 9.52 0.100 2.54 0.130 3.30 0.015 0.38 0.030 0.76 0.110 2.79 0.140 3.56 0.090 2.29 0.110 2.79 0.590 14.99 0.630 16.00 0.008 0.20 0.012 0.30 0.015 0.38 0.021 0.53 28pin pkg 13 equal spaces at .100 .010 tna note: pins 2, 3, 19 and 23 are missing by design. |
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